PROCESS FOR MANUFACTURING INTEGRATED ELECTRONIC DEVICES, IN PARTICULAR CMOS DEVICES USING A BORDERLESS CONTACT TECHNIQUE
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United States of America Patent
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Issued Date -
Dec 1, 2016
app pub date -
Dec 11, 2015
filing date -
Dec 11, 2015
priority date (Note) -
Abandoned
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Abstract
For manufacturing an integrated electronic device, a protection layer, of a first material, is formed over a body having a non-planar surface; a first dielectric layer, of a second material, is formed over the protection layer, the second material being selectively etchable with respect to the first material; an intermediate layer, of a third material, is formed over the first dielectric layer, the third material being selectively etchable with respect to the second material; a second dielectric layer, of a fourth material, is formed over the intermediate layer, the fourth material being selectively etchable with respect to the third material; vias are formed through the second dielectric layer, the intermediate layer, the first dielectric layer, and the protection layer; and electrical contacts, of conductive material, are formed in the vias.
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