MEMORY CHIP AND STACK TYPE SEMICONDUCTOR APPARATUS INCLUDING THE SAME
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United States of America Patent
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Dec 8, 2016
app pub date -
Sep 23, 2015
filing date -
Jun 4, 2015
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Abstract
A memory chip may include a plurality of channels including a plurality of memory banks and having a separate input/output interface, and each of the plurality of channels may be configured to simultaneously latch compression data groups obtained by compressing respective unit data groups outputted from the plurality of memory banks, sequentially output latched data as test read data according to a read start signal or a read end signal, and generate the read end signal which defines that final data output has ended.
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