Power on reset circuit applied to gate driver of display apparatus
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United States of America Patent
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Apr 24, 2018
Issued Date -
N/A
app pub date -
May 25, 2016
filing date -
Jun 2, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A power on reset circuit applied to a gate driver of a display apparatus is disclosed. The power on reset circuit is coupled between an operating voltage and a ground terminal. The power on reset circuit includes an output terminal, a first transistor, a second transistor, a resistor, and a buffer circuit. The first transistor is coupled between the operating voltage and a first node. A gate of first transistor is coupled to the first node. The second transistor is coupled between the operating voltage and the first node. A gate of second transistor is coupled to the ground terminal. The resistor is coupled between the first node and ground terminal. The buffer circuit is coupled between the first node and output terminal and outputs a reset signal through the output terminal. A second threshold voltage of second transistor is larger than a first threshold voltage of first transistor.
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