MEMORY SYSTEM AND METHOD OF OPERATING AND TESTING THE MEMORY SYSTEM
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United States of America Patent
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Issued Date -
Dec 15, 2016
app pub date -
Nov 11, 2015
filing date -
Jun 12, 2015
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Abstract
A memory system may include a plurality of chips configured to have an operation speed of a predetermined target speed or less. The memory system may include an error correction code (ECC) circuit configured to correct an error of each chip having an operation speed of higher than the target speed from among the plurality of chips.
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