Split-level history buffer in a computer processing unit
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United States of America Patent
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Mar 26, 2019
Grant Date -
Dec 22, 2016
app pub date -
Jun 16, 2015
filing date -
Jun 16, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A split level history buffer in a central processing unit is provided. A history buffer is partitioned into a first portion and a second portion, wherein the first portion includes a first tagged instruction. A result is generated for the first tagged instruction. A determination whether a second tagged instruction is to be stored in the first portion of the history buffer is made. Responsive to the determination that the second tagged instruction is to be stored in the first portion of the history buffer, the first tagged instruction and the generated result for the first tagged instruction is written to the second portion of the history buffer.
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