Low parasitic capacitance and resistance finFET device
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United States of America Patent
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Aug 6, 2019
Grant Date -
Dec 22, 2016
app pub date -
Jun 16, 2015
filing date -
Jun 16, 2015
priority date (Note) -
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Abstract
Described herein is a semiconductor structure and method of manufacture. The semiconductor structure includes a plurality of semiconductor fins on a substrate and a plurality of raised active regions, wherein each raised active region is located on sidewalls of a corresponding semiconductor fin among said plurality of semiconductor fins. The raised active regions are laterally spaced from any other of the raised active regions. Each raised active region comprises angled sidewall surfaces that are not parallel or perpendicular to a topmost horizontal surface of said substrate. The raised active regions are silicon germanium (SiGe). The semiconductor structure includes a metal semiconductor alloy region contacting at least said angled sidewall surfaces of at least two adjacent raised active regions. The semiconductor alloy region includes a material selected from the group consisting of nickel silicide, nickel-platinum silicide and cobalt silicide.
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