Instruction and logic for characterization of data access

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United States of America Patent

PATENT NO 9910669
SERIAL NO

14752014

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A processor includes a front end to receive an instruction, a decoder to decode the instruction, a core to execute the first instruction, and a retirement unit to retire the first instruction. The core includes logic to execute the first instruction, including logic to repeatedly record a translation lookaside buffer (TLB) until a designated number of records are determined, and flush the TLB after a flush interval.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Doshi, Kshitij A Chandler, US 143 1020
Hughes, Christopher J Santa Clara, US 196 2162

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