Techniques to wake-up dependent instructions for back-to-back issue in a microprocessor
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United States of America Patent
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Sep 18, 2018
Grant Date -
Dec 29, 2016
app pub date -
Aug 24, 2015
filing date -
Jun 26, 2015
priority date (Note) -
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Abstract
Techniques are disclosed for back-to-back issue of instructions in a processor. A first instruction is stored in a queue position in an issue queue. The issue queue stores instructions in a corresponding queue position. The first instruction includes a target instruction tag and at least a source instruction tag. The target instruction tag is stored in a table storing a plurality of target instruction tags associated with a corresponding instruction. Each stored target instruction tag specifies a logical register that stores a target operand. Upon determining, based on the source instruction tag associated with the first instruction and the target instruction tag associated with a second instruction, that the first instruction is dependent on the second instruction, a pointer to the first instruction is associated with the second instruction. The pointer is used to wake up the first instruction upon issue of the second instruction.
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