CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM

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United States of America Patent

SERIAL NO

15262178

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Abstract

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A cache memory system has a group of layered memories has two or more memories having different characteristics, an access information storage which stores address conversion information from a virtual address into a physical address, and stores at least one of information on access frequency or information on access restriction, for data to be accessed with an access request, and a controller to select a specific memory from the group of layered memories and perform access control, based on at least one of the information on access frequency and the information on access restriction in the access information storage, for data to be accessed with an access request from the processor, wherein the information on access restriction in the access information storage comprises at least one of read-only information, write-only information, readable and writable information, and dirty information indicating that write-back to a lower layer memory is not yet performed.

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Patent Owner(s)

Patent OwnerAddress
KABUSHIKI KAISHA TOSHIBA1-1 SHIBAURA 1-CHOME MINATO-KU TOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
FUJITA, Shinobu Tokyo, JP 110 1381
TAKEDA, Susumu Kawasaki, JP 47 411

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