Self aligned via in integrated circuit

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9768113
APP PUB NO 20160379929A1
SERIAL NO

15152981

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ATTORNEY / AGENT: (SPONSORED)

Importance

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Abstract

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A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION;STMICROELECTRONICS, INC.;TOKYO ELECTRON LIMITED

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Feurprier, Yannick Watervliet, US 17 321
Lee, Joe Albany, US 45 355
Liebmann, Lars W Poughquag, US 124 3874
Mignot, Yann Slingerlands, US 119 279
Spooner, Terry A Clifton Park, US 91 1106
Trickett, Douglas M Altamont, US 19 720
Yilmaz, Mehmet Ankara, TR 9 23

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