Thyristor Memory Cell with Gate in Trench Adjacent the Thyristor

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Jun 29, 2016
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Jun 29, 2015

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Abstract

A volatile memory array using vertical thyristors with gates, NMOS or PMOS, in trenches adjacent the thyristors is disclosed together with methods of fabricating the array.

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TC LAB INC	777 FIRST STREET PBM #138 GILROY CA 95020

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Inventor Name	Address	# of filed Patents	Total Citations
Axelrad, Valery	Woodside, US	40	245
Bateman, Bruce L	Fremont, US	42	210
Cheng, Charlie	Los Altos, US	41	189
Luan, Harry	Saratoga, US	56	221

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Thyristor Memory Cell with Gate in Trench Adjacent the Thyristor

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United States of America Patent

15197640

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15197640

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