Reduced current memory device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 10224100
APP PUB NO 20170004883A1
SERIAL NO

15100167

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Abstract

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A memory device includes a local bit line coupled to a plurality of memory cells and a global bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path is active in at least one of a set operation or a forming operation and the second path is active in a reset operation. A select device to select a memory element includes a drain having a first doping level and a source having a second doping level lower than the first doping level, wherein the device is configured to provide a first on impedance or a second on impedance to the resistive memory element in response to a control signal.

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Patent Owner(s)

  • RAMBUS INC.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bateman, Bruce L Fremont, US 42 199
Haukness, Brent S Monte Sereno, US 39 554
Sekar, Deepak Chandra San Jose, US 57 989

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