CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
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United States of America Patent
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Issued Date -
Jan 12, 2017
app pub date -
Jun 13, 2016
filing date -
Jul 6, 2015
priority date (Note) -
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Abstract
A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.
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