METHOD FOR PRODUCING A HIGH-VOLTAGE TRANSISTOR WITH REDUCED FOOTPRINT, AND CORRESPONDING INTEGRATED CIRCUIT
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United States of America Patent
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app pub date -
Mar 14, 2016
filing date -
Jul 8, 2015
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Abstract
An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.
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