Method of manufacturing semiconductor memory device having charge accumulation layer positioned between control gate electrode and semiconductor layer
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United States of America Patent
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Oct 17, 2017
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Mar 16, 2016
filing date -
Jul 16, 2015
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Abstract
According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.
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