Memory system, information processing system, and host device outputting debugging information through a host interface

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United States of America Patent

PATENT NO 10089212
APP PUB NO 20170024266A1
SERIAL NO

15066664

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Abstract

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An embodiment provides a memory system connectable to a host device. The memory system includes a host interface configured to receive a read command and a write command and a first non-volatile memory. In addition, the memory system includes a debug unit configured to collect debugging information when a processor executes firmware. The debug unit is capable of outputting the debugging information to a buffer area of the host device through the host interface.

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Patent Owner(s)

  • TOSHIBA MEMORY CORPORATION

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Iwai, Daisuke Yokohama, JP 52 266

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