Masking a power state of a core of a processor

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9710041
APP PUB NO 20170031412A1
SERIAL NO

14812056

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Abstract

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In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Choubal, Ashish V Austin, US 30 493
Garg, Vivek Folsom, US 94 1049
Gendler, Alexander Kiriat Motzkin, IL 85 285
Hallnor, Erik G Beaverton, US 10 85
Mulla, Dean Saratoga, US 19 512
Novakovsky, Larisa Haifa, IL 33 138
Sistla, Krishnakanth V Beaverton, US 96 793
Weier, Kimberly C Austin, US 6 80

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