SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF
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United States of America Patent
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Feb 2, 2017
app pub date -
Feb 22, 2016
filing date -
Jul 31, 2015
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Abstract
A semiconductor memory apparatus includes a normal write pulse generator configured to generate a normal write pulse in a normal operation, a test write pulse generator configured to repeatedly generate a test write pulse a preset number of times in a test operation, and a selector configured to provide the normal write pulse to a memory cell in the normal operation and provide the test write pulse to the memory cell in the test operation.
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