Integrated circuit having strained fins on bulk substrate and method to fabricate same
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United States of America Patent
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Apr 18, 2017
Issued Date -
N/A
app pub date -
May 2, 2016
filing date -
Jul 29, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A method includes forming a set of fins composed of a first semiconductor material. The method further heats the set of fins to condense the fins and cause growth of a layer of oxide on vertical sidewalls thereof, masking a first sub-set of the fins, forming a plurality of voids in the oxide by removing a second sub-set of fins, where each void has a three-dimensional shape and dimensions that correspond to a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set, and epitaxially growing in the voids a third sub-set of fins. The third sub-set of fins is composed of a second semiconductor material that differs from the first semiconductor material. Each fin of the third subset has a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set. At least one structure formed by the method is also disclosed.
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