Hybrid subtractive etch/metal fill process for fabricating interconnects

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United States of America Patent

PATENT NO 9653395
SERIAL NO

15157906

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Abstract

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In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bruce, Robert L White Plains, US 71 291
Fritz, Gregory M Wakefield, US 35 370
Joseph, Eric A White Plains, US 95 824
Miyazoe, Hiroyuki White Plains, US 103 888

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