Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof
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United States of America Patent
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Jan 30, 2018
Issued Date -
N/A
app pub date -
Nov 9, 2016
filing date -
May 19, 2014
priority date (Note) -
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Abstract
An integrated circuit includes a plurality of logic tiles, arranged in an array, wherein, during operation, each logic tile is configurable to connect with at least one logic tile that is adjacent thereto, and wherein each logic tile includes: clock distribution and transmission circuitry, configurable to (i) receive at least one tile input clock signal from one or more logic tiles which is/are adjacent thereto and (ii) to transmit at least one tile output clock signal to one or more logic tiles which is/are adjacent thereto; tile clock generation circuitry which is configurable to generate at least one tile clock using or based on the at least one input clock signal; circuitry, coupled to clock distribution and transmission circuitry, to disable circuitry of the clock distribution and transmission circuitry; and logic circuitry to perform operations using or based on at least one tile clock.
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