Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing
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United States of America Patent
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app pub date -
Sep 8, 2016
filing date -
Jan 9, 2007
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Abandoned
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Abstract
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
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