Multi-level flash storage device with minimal read latency
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United States of America Patent
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Dec 5, 2017
Grant Date -
Mar 2, 2017
app pub date -
Aug 28, 2015
filing date -
Aug 28, 2015
priority date (Note) -
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Abstract
A memory system, non-volatile solid-state memory, and a method of efficiently reading data from a flash memory array are disclosed. The disclosed memory system includes a flash memory array having a plurality of memory cells that store data therein, each of the plurality of memory cells being configured to store at least two bits per cell and being organized into pages, and a controller configured to read any bit of data from a page of the flash memory array by applying a single threshold voltage to the flash memory array. Reading data from the flash memory array with a single threshold greatly decreases the latency associated with the read operation.
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