Semiconductor memory device having variable resistance elements provided at intersections of wiring lines
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United States of America Patent
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Nov 7, 2017
Issued Date -
N/A
app pub date -
Mar 22, 2016
filing date -
Aug 31, 2015
priority date (Note) -
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Abstract
According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.
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