Semiconductor storage device and control method of semiconductor storage device with detecting levels of a multi-ary signal
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United States of America Patent
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Jan 2, 2018
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N/A
app pub date -
Dec 10, 2015
filing date -
Sep 9, 2015
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Abstract
According to one embodiment, there is provided a semiconductor storage device including N word lines, M bit lines, multiple memory cells, and a read circuit. N is an integer of four or greater. M is an integer of two or greater. The M bit lines intersect with the word lines. The multiple memory cells are placed at positions where the word lines and the bit lines intersect. The memory cell stores binary data. The read circuit is connected to the M bit lines. The read circuit is able to detect levels of a multi-ary signal.
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