Importance

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Abstract

Embodiments herein provide for avoiding ID collisions in a memory device. In one embodiment, a memory device includes slave logic operable to receive I/O commands from a plurality of master components and a memory controller operable to process the I/O commands from the master components to operate on data in the memory. Each I/O command comprises an ID assigned by its originating master component. The slave logic is further operable to determine the ID of a first I/O command from a first of the master components, to receive a second I/O command from a second of the master components having a same ID as the first I/O command while the first I/O command is being processed by the memory controller, and to stall the second I/O command until the first I/O command is complete while allowing other I/O commands with other IDs to access the memory.

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First Claim