Wafer-level flipped die stacks with leadframes or metal foil interconnects
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United States of America Patent
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May 30, 2017
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N/A
app pub date -
Nov 3, 2016
filing date -
Jul 17, 2015
priority date (Note) -
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Abstract
An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.
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