Semiconductor memory devices including a memory cell array and stepped wiring portions, and manufacturing methods thereof
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United States of America Patent
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Jan 22, 2019
Grant Date -
Mar 16, 2017
app pub date -
Sep 2, 2016
filing date -
Sep 11, 2015
priority date (Note) -
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Abstract
A semiconductor memory device according to an embodiment includes a memory cell array that includes memory cells and a plurality of first conducting layers. The memory cells are arrayed in a three-dimensional manner. The first conducting layers are connected to the memory cells and are arrayed in a laminating direction. Stepped wiring portion includes a plurality of second conducting layers. The plurality of second conducting layers connect the first conducting layers and external circuits. At least one of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the first side portion side. Other ones of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the second side portion side.
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