CONFIGURING FAST MEMORY AS CACHE FOR SLOW MEMORY

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United States of America Patent

APP PUB NO 20170083444A1
SERIAL NO

14862030

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Abstract

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A cache controller to configure a portion of a first memory as cache for a second memory responsive to an indicator of locality of memory access requests to the second memory. The indicator of locality determines a probability that a location of a memory access request to the second memory is predictable based upon at least one previous memory access request. The cache controller may determine a size of the cache based on a value of the indicator of locality or modify the size of the cache in response to changes in the value of the indicator of locality.

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Patent Owner(s)

Patent OwnerAddress
ADVANCED MICRO DEVICES INC2485 AUGUSTINE DRIVE SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dev, Kapil Austin, US 13 50
Eckert, Yasuko Bellevue, US 96 782
Kalamatianos, John Boxborough, US 95 524
Meswani, Mitesh R Austin, US 15 116
Paul, Indrani Austin, US 80 382
Roberts, David A Sunnyvale, US 243 3897

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