III-V MOSFET with self-aligned diffusion barrier
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United States of America Patent
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Dec 26, 2017
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app pub date -
Apr 22, 2016
filing date -
Sep 30, 2015
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Abstract
A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
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