Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity
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United States of America Patent
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Sep 19, 2017
Issued Date -
Mar 30, 2017
app pub date -
Sep 30, 2015
filing date -
Sep 30, 2015
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Abstract
A replacement gate FinFET manufacturing process in which the source/drain regions, gate structure and gate spacer are all defined by utilizing a single sidewall image transfer technique is provided. In the present application, the source/drain region (i.e., area) are defined by a mandrel structure, while the area for the functional gate structure are defined by the distance between spacers that are located on a pair of neighboring mandrel structures. The gate spacer is defined by the spacer present on the mandrel structures. In some embodiments, semiconductor fin erosion due to gate and gate spacer formation can be reduced or even eliminated.
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