Memory module with reduced read/write turnaround overhead
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United States of America Patent
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Mar 26, 2019
Grant Date -
Apr 6, 2017
app pub date -
May 26, 2015
filing date -
May 27, 2014
priority date (Note) -
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Abstract
A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.
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