Buffer circuit and electronic device using same
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United States of America Patent
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May 22, 2018
Issued Date -
N/A
app pub date -
May 6, 2015
filing date -
May 6, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A buffer circuit includes a buffer group including an odd number of cascade buffers, where the buffers may be different from each other; a PMOS transistor and an NMOS transistor; where a source of the PMOS transistor is coupled to a power source, a drain thereof is connected to an output terminal of the buffer group, and a gate thereof is connected to an input terminal of the buffer group; a source of the NMOS transistor is coupled to ground, a drain thereof is connected to the output terminal of the buffer group, and a gate thereof is connected to the input terminal of the buffer group.
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