Bit line clamp voltage generator for STT MRAM sensing
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United States of America Patent
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Dec 26, 2017
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N/A
app pub date -
Jan 12, 2017
filing date -
Aug 11, 2015
priority date (Note) -
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Abstract
A bit line clamp voltage generator circuit for a Spin Torque Transfer Magnetoresistive Random Access Memory is provided. The circuit includes a negative channel Field Effects Transistor having a source, a drain, and a gate, the gate being connected to the drain. The circuit further includes a resistor Rs having a first end connected to a first voltage and a second end connected to the source. The circuit also includes a resistor Rd having a first end connected to a second voltage and a second end connected to the drain to form an output node for outputting a bit line clamp voltage.
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