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Abstract

A method for packaging integrated circuits includes providing a substrate array having (i) multiple individual substrates, each of which has bottom contact pads and corresponding conductive traces and (ii) plating busses located between adjoining ones of the substrates and electrically connected to the bottom contact pads by way of the traces. The method further includes (i) forming slots in the substrate array by removing portions of the plating busses connected to the traces while leaving corner attachment zones connecting adjacent individual substrates, (ii) attaching and electrically connecting dies to the substrates, (iii) encapsulating the dies, (iv) electrically and functionally testing the assemblies, and then, after the testing, (v) singulating the assemblies, which yields individual IC devices corresponding to the individual substrates.

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First Claim