P-FET with strained silicon-germanium channel

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United States of America Patent

PATENT NO 10079181
APP PUB NO 20170125303A1
SERIAL NO

15402265

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A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINE CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cheng, Kangguo Schenectady, US 3073 29791
Khakifirooz, Ali Los Altos, US 842 11906
Reznicek, Alexander Troy, US 1407 11211
Shahidi, Ghavam G Pound Ridge, US 396 8125

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