Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same
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United States of America Patent
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Sep 26, 2017
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app pub date -
Jan 10, 2017
filing date -
Oct 9, 2015
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Abstract
A structure includes an off-axis Si substrate with an overlying s-Si1−xGex layer and a BOX between the off-axis Si substrate and the s-Si1−xGex layer. The structure further includes pFET fins formed in the s-Si1−xGex layer and a trench formed through the s-Si1−xGex layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si1−xGex layer has a value of x that results from a condensation process that merges an initial s-Si1−xGex layer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed.
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