Asymmetric high-k dielectric for reducing gate induced drain leakage

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United States of America Patent

PATENT NO 9859122
SERIAL NO

15406096

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An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

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  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chou, Anthony I Beacon, US 82 597
Kumar, Arvind Beacon, US 310 3377
Lin, Chung-Hsun White Plains, US 170 2380
Narasimha, Shreesh Beacon, US 133 1488
Ortolland, Claude Peekskill, US 30 297
Shaw, Jonathan T Rego Park, US 16 239

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