Memory Controller For Selective Rank Or Subrank Access
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United States of America Patent
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app pub date -
Oct 17, 2016
filing date -
May 2, 2006
priority date (Note) -
Abandoned
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Abstract
A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.
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