Implementing hardware accelerator for storage write cache management for identification of data age in storage write cache

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United States of America Patent

PATENT NO 9940255
SERIAL NO

14939961

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Abstract

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A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs data age identification in storage write cache substantially without firmware involvement for greatly enhancing performance.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINE CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bakke, Brian E Rochester, US 56 610
Edwards, Joseph R Rochester, US 17 38
Galbraith, Robert E Rochester, US 37 792
Gerhard, Adrian C Rochester, US 81 586
Moertl, Daniel F Rochester, US 82 1165
Radhakrishnan, Gowrisankar Colorado Springs, US 40 390
Weckwerth, Rick A Oronoco, US 33 403

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