Memory control component with inter-rank skew tolerance
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United States of America Patent
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Nov 14, 2017
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app pub date -
Dec 26, 2016
filing date -
Mar 19, 2012
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Abstract
In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
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