Semiconductor devices having charged punch-through stopper layer to reduce punch-through and methods of manufacturing the same

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United States of America Patent

PATENT NO 10644103
SERIAL NO

15296448

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Abstract

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Provided are a semiconductor device having a charged punch-through stopper (PTS) layer to reduce punch-through and a method of manufacturing the same. In an embodiment, the semiconductor device may include a fin structure formed on a substrate; an isolation layer formed on the substrate, wherein a portion of the fin structure above the isolation layer acts as a fin of the semiconductor device; a charged PTS layer formed on side walls of a portion of the fin structure beneath the fin; and a gate stack formed on the isolation layer and intersecting the fin. The semiconductor device may be an n-type device or a p-type device. For the n-type device, the PTS layer may have net negative charges, and for the p-type device, the PTS layer may have net positive charges.

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Patent Owner(s)

  • INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Wei, Xing Beijing, CN 103 633
Zhu, Huilong Poughkeepsie, US 690 12414

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