Clock and data recovery having shared clock generator
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United States of America Patent
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Sep 19, 2017
Issued Date -
N/A
app pub date -
Oct 31, 2016
filing date -
Mar 13, 2012
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Abstract
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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