FREQUENCY DOUBLER HAVING OPTIMIZED HARMONIC SUPPRESSION CHARACTERISTICS
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United States of America Patent
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Issued Date -
May 18, 2017
app pub date -
Oct 20, 2016
filing date -
Nov 18, 2015
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Abstract
Disclosed is a frequency doubler which controls a magnitude of a signal supplied to a virtual ground by adjusting a gain of one-side transistor among transistors receiving differential input signals when outputting a frequency multiplied LO signal through the virtual ground by amplifying the input differential signals by using a differential circuit structure to minimize undesired harmonics characteristics in a frequency doubled signal output by making the magnitudes of two differential signals be the same as each other.
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