Multi-bit flip-flop with soft error suppression
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United States of America Patent
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Jun 20, 2017
Grant Date -
May 25, 2017
app pub date -
Jun 3, 2016
filing date -
Nov 23, 2015
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Abstract
A multi-bit flip-flop includes at least two storage stages. Each of the storage stages includes redundant latches to suppress state corruptions resulting from soft error upset at the storage stage. In addition, the multi-bit flip-flop includes a split clock path that routes different shared clock signals that control the timing of the latches. The shared split clock path reduces or eliminates the impact of soft errors on the clock signals, thereby further limiting the impact of such errors on data stored at the flip-flop. In particular, the split clock path can be distributed over disparate cells in a layout of multi-bit flip-flop, thereby reducing the likelihood that a transient charge will cause a soft error in all paths of the split clock path.
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