SEMICONDUCTOR PACKAGES
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United States of America Patent
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Issued Date -
Jun 1, 2017
app pub date -
Apr 12, 2016
filing date -
Dec 1, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor package includes a first die including first chip pads disposed in a first chip pad region, first connecting pads spaced apart from the first chip pad region a predetermined distance and gathered in a first connecting pad region, and first redistribution layer patterns connecting the first chip pads to the first connecting pads, a second die including second chip pads disposed in a second chip pad region on the chip, second connecting pads spaced apart from the second chip pad region a predetermined distance and disposed in a second connecting pad region, and second redistribution layer patterns connecting the second chip pads to the second connecting pads, and a first semiconductor chip disposed below the first die and the second die, and electrically connected to the first connecting pads and the second connecting pads. The second connecting pad region is disposed adjacent to the first connecting pad region.
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