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Abstract

There is provided a phase synchronization circuit including: a generation circuit to which an input clock signal is input, and configured to shift the input clock signal by intervals at which numbers of clocks of the input clock signal become equal so as to generate a plurality of pulse signals; a plurality of counter circuits each configured to measure pulse intervals of each of the plurality of pulse signals generated by the generation circuit, respectively; an average value calculation circuit configured to calculate an average value of measured values by the plurality of counter circuits; a frequency calculation circuit configured to calculate a frequency of the input clock signal from the average value calculated by the average value calculation circuit; and a phase locked loop (PLL) circuit configured to perform a phase synchronization processing on the input clock signal, based on the frequency calculated by the frequency calculation circuit.

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First Claim