COMPRESSING DETECTED CURRENT AND PRECEDING INSTRUCTIONS WITH THE SAME OPERATION CODE AND OPERAND PATTERNS

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United States of America Patent

SERIAL NO

15448280

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Abstract

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A processor accesses memory storing a compressed instruction sequence that includes compression information indicating that an instruction that with respect to the preceding instruction, has identical operation code and operand continuity is compressed. The processor includes a fetcher that fetches a bit string from the memory and determines whether the bit string is a non-compressed instruction, where if so, transfers the given bit string and if not, transfers the compression information; and a decoder that upon receiving the non-compressed instruction, holds in a buffer, instruction code and an operand pattern of the non-compressed instruction and executes processing to set to an initial value, the value of an instruction counter that indicates a count of consecutive instructions having identical operation code and operand continuity, and upon receiving the compression information, restores the instruction code based on the instruction code held in the buffer, the instruction counter value, and the operand pattern.

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Patent Owner(s)

Patent OwnerAddress
FUJITSU LIMITEDKAWASAKI-SHI KANAGAWA 211-8588
FUJITSU SEMICONDUCTOR LIMITED2-10-23 SHIN-YOKOHAMA KOHOKU-KU YOKOHAMA-SHI KANAGAWA 222-0033

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ito, Makiko Kawasaki, JP 16 47
Tomono, Mitsuru Kawasaki, JP 31 32
Uehara, Hiroya Yokohama, JP 2 1

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