MEMORY REFRESH METHOD AND DEVICES

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United States of America Patent

SERIAL NO

15391295

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Abstract

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The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INC1050 ENTERPRISE WAY SUITE 700 SUNNYVALE CA 94089

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brooks, John San Jose, US 30 500
Perego, Richard Thornton, US 11 702
Vogelsang, Thomas Mountain View, US 163 1479

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