System and method for performing memory operations on RRAM cells

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United States of America Patent

PATENT NO 10236059
APP PUB NO 20170178723A1
SERIAL NO

15393233

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Abstract

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A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.

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Patent Owner(s)

  • HEFEI RELIANCE MEMORY LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Haukness, Brent Steven Monte Sereno, US 38 380

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